Microelectronic features are typically formed in and/or on wafers or other types of workpieces by selectively removing material from the wafer and filling the resulting features with dielectric, semiconductive, and/or conductive materials. Photolithographic processes are generally used to transfer intricate patterns onto very small areas of the wafers. A typical photolithographic process includes depositing a layer of radiation-sensitive photoresist material on the wafer, positioning a reticle having a patterned mask over the photoresist, and then passing an imaging radiation through a patterned area of the reticle to expose the photoresist in the configuration of the patterned mask. A developer, such as an aqueous base or a solvent, is used to remove either the irradiated areas or the masked areas of the photoresist. For example, the exposed portions of the photoresist can change from being generally soluble to become generally insoluble in the developer such that the developer removes the masked portions of the resist layer. Alternatively, the radiation can change a different type of photoresist from being generally insoluble in the developer to be generally soluble such that the exposed portions of the photoresist are removed when the wafer contacts the developer.
Existing lithography processes are capable of creating very complex patterns of extremely small features across the surface of a wafer to form the trenches, vias, holes, implant regions, and other features on a wafer. In a typical application, a lithographic tool transfers the pattern in the reticle to the wafer by scanning or stepping the pattern across precise areas of the wafer. As microelectronic devices become more complex, there is a drive to continually decrease the size of the individual features and increase the density of the features across the wafer. This significantly increases the complexity of lithographic processing because it is increasingly difficult to accurately focus the pattern onto the surface of the wafer. In many applications, the depth of field for focusing the pattern on the wafer is so small that slight variations in the wafer surface can adversely affect the quality of the pattern transferred to the wafer.
FIG. 1A is a side cross-sectional view of a wafer 10 having a photoresist layer 11 exposed to a selected radiation. Various fabrication processes performed on the wafer 10 (e.g., etching processes, chemical-mechanical planarization, plating processes, and/or film depositions) can form relatively large surface variations on the wafer 10 (e.g., up to about 6000 Angstroms), particularly in the area 2-5 mm from the edge of the wafer 10. The edge of the wafer 10, for example, includes a topographical feature 20. As mentioned above, the depth of field for focusing the pattern on the wafer 10 is so small that slight variations in the surface topography (e.g., a topographical feature 20) can adversely affect the depth of focus of the radiation incident upon the wafer 10 in such areas. The edges of the photoresist layer 11 remaining on the wafer 10 (after the wafer is exposed to the developer) often become indistinct because of such topographical irregularities. This in turn can adversely affect the definition of the microelectronic features formed on and/or in the wafer 10.
One conventional approach addressing the depth of focus problem described above is to use a straight line “best fit” model to compensate for various topographical features and/or irregularities on the wafer 10. This approach includes adjusting the focus height (i.e., the z-height) of the radiation beam impinging on the wafer 10. In FIG. 1A, for example, an image plane 30 of the beam is adjusted upwardly in an attempt to compensate for the topographical feature 20. More particularly, the image plane 30 is moved upwardly so that it is approximately equidistant from the top. planar surface of the wafer 10 and the top of the topographical feature 20. The z-height variation shown in FIG. 1A, however, is a global variation that is applied across the entire exposure field or exposure slit, in the case of a scanner. Further, the “best fit” shown in FIG. 1A only compensates for the topographical feature 20 at the edge of the wafer 10 and may not compensate for many other topographical features and/or irregularities on the wafer 10. Thus, the compensation for the topographical feature 20 at the edge of the wafer 10 generally negatively affects the rest of the exposure field or slit on the wafer 10.
Another approach to addressing the foregoing problem is to tilt the wafer relative to the image plane 30 of the beam. Referring to FIG. 1B, for example, the wafer 10 is tilted relative to the image plane 30 to “best fit” the image plane to the wafer. This approach, however, can also negatively affect the rest of the exposure field or slit. The linear image plane 30, for example, still does not conform to the surface of the wafer 10 or the topographical feature 20, resulting in a number of local z-height variations 40. In many cases, the local z-height variations 40 can be significant. Accordingly, there is a need to improve the process for irradiating microfeature workpieces.